1. Technical Field
The present invention relates to a square spacer and an associated method of fabrication.
2. Related Art
Sidewall features known as "spacers" are used in electronic packages and are formed in abutment with such electronic features as gates, conductive lines, transistors, and inherent topography. Such a feature is characterized by a vertical wall against which a spacer can be formed. In particular, a stack of spacers are commonly formed as arrayed in a horizontal direction with a first spacer of the stack abutting the vertical wall of the feature. Each spacer in the stack is parallel to the vertical wall and more distant from the vertical wall than the immediately preceding spacer. An array of 1 to 3 spacers in such a stack is common. With current methods of spacer formation, a spacer formed in abutment with a wall does not have a horizontal top surface but rather has a top surface with a rounded corner on that portion of the top surface that is most distant from the wall. The rounded corner results from a plasma etching process that utilizes isotropic distributions of particles, such as ionized plasma particles, for etching a material from which the spacer is formed, as well as from the topography of the material to be etched. Unfortunately, the rounded corner of a given spacer reduces the vertical height of the side of the spacer that includes the rounded corner. As a result, less vertical height is available for the next spacer in the stack in the horizontal direction away from the feature; i.e., the height of successive spacers in the stack are reduced. For example, if the first spacer (i.e., the spacer abutting the feature) in the stack is 2000 .ANG. high, then the second and third spacers in the stack may be limited to vertical heights of only 1400 .ANG. and 1000 .ANG., respectively. Even worse, the width of successive spacers in the stack are also reduced because fabrication methods generally limit a spacer width to be no greater than about two-thirds of the spacer height. Thus, current fabrication methods limit both successive vertical heights and the total cumulative width of a stack of spacers that abut a feature of the electronic package. A particular disadvantage associated with the limitation on successive vertical height is that insulative spacers between conductive structure on the electronic package may have insufficient height or width to prevent undesired diffusion of conductive material from one conductive structure to another, resulting in shorting over the spacer.
A method is needed for fabricating a square spacer having a flat horizontal top surface.